module cpsr(
  input            clk,
  input            rst,
  input            nzcv_we,
  input      [3:0] nzcv_d,
  input      [2:0] aif_we,
  input      [2:0] aif_d,
  input            mode_we,
  input      [4:0] mode_d,
  output reg [3:0] nzcv,
  output reg [2:0] aif,
  output reg [4:0] mode
);

always @(posedge clk) begin
  if (rst) begin
    /* Disable IRQ, FIQ, Imprecise Aborts */
    aif  <= 3'b111;
    mode <= 5'b10011; // svc
  end else begin
    if (nzcv_we) nzcv <= nzcv_d;
    if (aif_we[2]) aif[2] <= aif_d[2];
    if (aif_we[1]) aif[1] <= aif_d[1];
    if (aif_we[0]) aif[0] <= aif_d[0];
    if (mode_we) mode <= mode_d;
  end
end

`ifndef SYNTHESIS

reg trace;

initial trace = $test$plusargs("trace") != 0;

always @(posedge clk) begin
  if (trace) begin
    if (nzcv_we) $display("%%cpsr_nzcv=%b", nzcv_d);
    if (aif_we[2]) $display("%%cpsr_a=%b" , aif_d[2]);
    if (aif_we[1]) $display("%%cpsr_i=%b" , aif_d[1]);
    if (aif_we[0]) $display("%%cpsr_f=%b" , aif_d[0]);
    if (mode_we) $display("%%cpsr_mode=%b", mode_d);
  end
end

`endif

endmodule
